1. Technical Field
The present invention relates in general to a system and method for an intelligent Direct Memory Access (DMA) controller with multi-dimensional “line-walking” functionality. More particularly, the present invention relates to a system and method for including an intelligent DMA controller into a computer system such that the intelligent DMA controller is able to independently retrieve data from a multi-dimensional array based upon a line description.
2. Description of the Related Art
Computer systems are becoming increasingly complex. The computer industry continues a long-standing trend of doubling overall performance every eighteen months in electronic components such as personal computers, personal data assistants (PDAs) and game consoles. This trend continues primarily due to the semiconductor industry producing integrated circuits whose performance is twice that of predecessor circuits.
Current architectures implement DMA controllers that retrieve spans of contiguous address space from memory, or disparate lists of spans of contiguous address space from memory. The retrieved data is then loaded into storage locations more “local” to the support processor, whereby the support processor may access the data using fewer access cycles (e.g. a cache). A challenge found, however is that this approach requires a user to specify exact address locations of each of the spans from which to retrieve the data.
When a processor requires the retrieval of data from a multi-dimensional array in main memory whose addresses are derived from traversing a line in space, a challenge found is that the processor's DMA controller requires the processor to provide address locations as to where to retrieve data.
In addition, the computer industry is increasing performance by developing multi-processor architectures that typically include a main processor and one or more support processors. The main processor typically loads and executes an operating system that invokes application programs and, in turn, the application programs use the support processors to offload highly computational tasks. The support processors typically include a basic DMA controller that reads from and writes to main memory in order to perform the support processor's assigned task. A challenge found, however, in multi-processor environments is that a support processor may require assistance from a main processor to stage data in L2 cache from a shared memory such that the support processor's basic DMA controller retrieves data in its correct order.
What is needed, therefore, is a system and method to provide a processor with the ability for its DMA controller to retrieve data based upon a line description without burdening the processor.